-------------------------------------------------------------------------------
-- register_rtl.vhd
-------------------------------------------------------------------------------
--
-- This file is part of SKUMLI.
-- Copyright (C) 2011 Davide Giuseppe Monaco (black.ralkass@gmail.com)
--
-- SKUMLI is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- SKUMLI is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with SKUMLI.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
architecture rtl of reg is
begin -- rtl

  sync: process (clk, rst, we)

    variable x : std_logic_vector(N - 1 downto 0);

  begin -- sync

    if rst = '1' then
      x := (others => '0');

    elsif clk'event and clk = '1' and we = '1' then
      x := din;

    end if;

    dout <= x;

  end process sync;
-------------------------------------------------------------------------------
end rtl;
